From what you wrote would I be correct is stating that if my current motherboard had 2 PCIe 3.0 X 16 slots that the "PCIe Bandwidth Utilization" would be about the same for both of these GPUs? And that the difference I am seeing is due to the second slot being a PCIe 2.0 X 16.
Yes and almost yes! For the 2nd question the different clock speeds of the GPU also have to be taken into account (as I did, approximately). But any further difference can be attributed to the PCIe slots.
And a PCIe 2 slot with 16 lanes electrically connected / being used would fare much better than yours, bus utilization should not be higher than twice of the PCIe 3 16x slot, probably even a bit less. But in your case only 4 of the possible 16 lanes are being used, which does hurt performance clearly.
From the images I posted and from your previous explanations I understand that the PCIe2 slot is operating at 4 lanes. You say that "PCIe 2 with 16 lanes ... would fare better than mine". From this statement I am getting the impression that something in my hardware configuration is throttling back the 2 GPUs performance, i.e., it should be performing better than it is. Am I correct? If so what could cause this? I am now thinking with the performance on this second card that I would be better off relocating it to the earlier PC where I would get better performance in the PCIe 2 X 16 slot since it would be the only GPU in the case. I do appreciate your time, effort and patience.
Quote:
Is that difference between "mechanically 16x" slots and how many lanes are actually being used clear now?
I suppose my confusion is due to not understanding the relationship of slots to lanes. By "mechanically 16x" you mean that there is physically 16 "slots" but only 4 are being used in my case. If so and as I asked earlier what would limit it to 4 lanes.
I suppose my confusion is due to not understanding the relationship of slots to lanes. By "mechanically 16x" you mean that there is physically 16 "slots" but only 4 are being used in my case. If so and as I asked earlier what would limit it to 4 lanes.
A slot is the big thing you can see on the motherboard to place a card in.
A lane is a full duplex serial data connection, having two wires for receiving and two for sending.
A slot contains connections available for some power-of-two number of lanes. The exact number is a design choice of the board manufacturer.
A PCIe link is a logical grouping of lanes.
A PCIe card gets allocated a link's worth of lanes during startup.
The allocation of lanes to links occurs during PnP setup, managed by the board's chipset ( South, or sometimes North, Bridge ) that contains the PCIe switching facility ( host adapter ). The PCIe switch/host negotiates with the all the cards in all the PCIe slots.
It's not necessarily the case that all lanes of a slot are used :
- a card may have fewer because the edge connector doesn't fill the slot, or doesn't have lane connections in some positions.
- a card may not be allocated to it's link all the lanes that it has. The card has to cope with it's link being throttled by the host.
Cheers, Mike.
( edit ) As regards :
Quote:
I was looking at an Asus motherboard that has 5 PCIe 3.0 X 16 slots.
the moot point becomes what is the host adapter's capacity to service these ? If you look at this Asus board specs ( clearly presented as the best thing since sliced bread ) you'll note a table of qualifying information about populating those slots :
.... so evidently you don't/won't get 5 x 16 = 80 lanes in practice, subsumed by the phrase 'adjust configurations'. One might deduce from this that the host switching can cope with up to 40 lanes. To be even more annoying I'll mention the config for that board's Intel chipset, to illustrate how many **actual** lanes for graphics get to the processor die itself.
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Robl, it's actually quite simple once you get your head around it. The mechanical size of a slot is really just how long it is. "Mechanically 16x" means it's as long as the usual slots for GPUs. But there are also shorter ones: 8x, 4x, 2x and even 1x. Picking some random Asus mainboard there are 2 PCIe slots "mechanically 16x": counting from the right it's the 2nd and 5th one. The 1st and 3rd are probably 1x, maybe 2x. You couldn't fit a GPU in there without damaging something. So the mechanical size of a PCIe slot tells you how much plastic there is to put some card into.
Now on to the electrical contacts: PCIe connections consist of lanes, which can be imagined as cables connecting both points (i.e. CPU and GPU). There can be several lanes operating in parallel, independently of each other to increase the overall bandwidth. But it's also OK for some device not to use all lanes - which is what we've been talking about.
In your case only 4 lanes are routed from the chipset to the "mechanically 16x" PCIe 2 slot, hence there are "just not enough cables" to use the contact pads on the GPU. That's OK from the mainboards point of view, as the chipset usually only has 4 lanes to spare (i.e. it's already doing all it can).
And there's nothing you could do about it apart from moving the GPU into a faster slot or putting a slower GPU into this slot, if you have one.
Dskagcommunity, peak efficiency of PC PSUs has never been at 80 - 90% as far as I can remember (mid '90s). It used to be around 50%, where the peak is stil to be found. But modern efficient PSUs show far flatter power-vs-load curves, so it's not as important to that 50% as it used to be.
I now have a handle on this discussion thanks to your last responses. Interesting Mike, the Asus mother board you referenced is the one I had alluded to in an earlier post. I had seen the data for that board but did not completely understand it. Now I do. It could have been a costly mistake based upon my earlier understanding. Like they say, "The only stupid question is the one that is not asked.". So let me ask one more. Would a SLI configuration on a board that supports SLI give any advantage. I know they are physically bridged by a flat ribbon cable, but do not understand the impact of joining two GPUs in that fashion.
Edit: looking at the data for the 5 slot 3.0 X 16 Asus board you posted Mike, I have answered my question regarding SLI with respect to performance.
It could have been a costly mistake based upon my earlier understanding.
I have made such a costly mistake, hence my prior research into the detail of the matter !! :-)
I'm not aware that SLI is relevant to E@H ...... anyone ???
Cheers, Mike.
( edit ) In addition to the lane count per link, there is also the speed of the lane ie. the clocking frequency of the LVDS ( Low Voltage Differential Signalling ) layer used. The problem with PCI, which is parallel hardware, was that the precise length of the signal lines comes into play at high clocking. One might send all signals ( of a parallel bus ) in clock sync from some source, but varying delays due to varying 'wire' lengths mean that some signal transitions arrive too late/early with respect to others, in order to be present as simultaneously valid at the destination. Some might 'miss the cut'. A pair of LVDS wires ( which constitute a receive or transmit portion of a full duplex serial connection ) carries no clocking signal per se. The PCIe standard mimics a parallel device by packetising data, in effect a form of multiplexing and demultiplexing. The assumption, and practice, is that the rather higher speed of the serial lanes outweighs the overhead of managing the packets.
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Count me in with three costly mistakes working to run the fastest AMD host on the project ;)
AFAIK, Dual Display or SLI doesn't do anything good for BOINC, rather the opposite (at least in the old days this caused the then-current BOINC Versions to detect & use only one card).
Nowadays, it shouldn't make any difference - but the recommendation remained to keep Dual Display/SLI disabled in the Video Driver settings to avoid any issues.
I would also think linking them together would cause a tiny bit of overhead that can be avoided no matter how small it is.
MrS RE: RE: From
)
MrS
From the images I posted and from your previous explanations I understand that the PCIe2 slot is operating at 4 lanes. You say that "PCIe 2 with 16 lanes ... would fare better than mine". From this statement I am getting the impression that something in my hardware configuration is throttling back the 2 GPUs performance, i.e., it should be performing better than it is. Am I correct? If so what could cause this? I am now thinking with the performance on this second card that I would be better off relocating it to the earlier PC where I would get better performance in the PCIe 2 X 16 slot since it would be the only GPU in the case. I do appreciate your time, effort and patience.
I suppose my confusion is due to not understanding the relationship of slots to lanes. By "mechanically 16x" you mean that there is physically 16 "slots" but only 4 are being used in my case. If so and as I asked earlier what would limit it to 4 lanes.
RE: I suppose my confusion
)
A slot is the big thing you can see on the motherboard to place a card in.
A lane is a full duplex serial data connection, having two wires for receiving and two for sending.
A slot contains connections available for some power-of-two number of lanes. The exact number is a design choice of the board manufacturer.
A PCIe link is a logical grouping of lanes.
A PCIe card gets allocated a link's worth of lanes during startup.
The allocation of lanes to links occurs during PnP setup, managed by the board's chipset ( South, or sometimes North, Bridge ) that contains the PCIe switching facility ( host adapter ). The PCIe switch/host negotiates with the all the cards in all the PCIe slots.
It's not necessarily the case that all lanes of a slot are used :
- a card may have fewer because the edge connector doesn't fill the slot, or doesn't have lane connections in some positions.
- a card may not be allocated to it's link all the lanes that it has. The card has to cope with it's link being throttled by the host.
Cheers, Mike.
( edit ) As regards :
the moot point becomes what is the host adapter's capacity to service these ? If you look at this Asus board specs ( clearly presented as the best thing since sliced bread ) you'll note a table of qualifying information about populating those slots :
.... so evidently you don't/won't get 5 x 16 = 80 lanes in practice, subsumed by the phrase 'adjust configurations'. One might deduce from this that the host switching can cope with up to 40 lanes. To be even more annoying I'll mention the config for that board's Intel chipset, to illustrate how many **actual** lanes for graphics get to the processor die itself.
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Robl, it's actually quite
)
Robl, it's actually quite simple once you get your head around it. The mechanical size of a slot is really just how long it is. "Mechanically 16x" means it's as long as the usual slots for GPUs. But there are also shorter ones: 8x, 4x, 2x and even 1x. Picking some random Asus mainboard there are 2 PCIe slots "mechanically 16x": counting from the right it's the 2nd and 5th one. The 1st and 3rd are probably 1x, maybe 2x. You couldn't fit a GPU in there without damaging something. So the mechanical size of a PCIe slot tells you how much plastic there is to put some card into.
Now on to the electrical contacts: PCIe connections consist of lanes, which can be imagined as cables connecting both points (i.e. CPU and GPU). There can be several lanes operating in parallel, independently of each other to increase the overall bandwidth. But it's also OK for some device not to use all lanes - which is what we've been talking about.
In your case only 4 lanes are routed from the chipset to the "mechanically 16x" PCIe 2 slot, hence there are "just not enough cables" to use the contact pads on the GPU. That's OK from the mainboards point of view, as the chipset usually only has 4 lanes to spare (i.e. it's already doing all it can).
And there's nothing you could do about it apart from moving the GPU into a faster slot or putting a slower GPU into this slot, if you have one.
MrS
Scanning for our furry friends since Jan 2002
Dskagcommunity, peak
)
Dskagcommunity, peak efficiency of PC PSUs has never been at 80 - 90% as far as I can remember (mid '90s). It used to be around 50%, where the peak is stil to be found. But modern efficient PSUs show far flatter power-vs-load curves, so it's not as important to that 50% as it used to be.
MrS
Scanning for our furry friends since Jan 2002
MrS/Mike, I now have a
)
MrS/Mike,
I now have a handle on this discussion thanks to your last responses. Interesting Mike, the Asus mother board you referenced is the one I had alluded to in an earlier post. I had seen the data for that board but did not completely understand it. Now I do. It could have been a costly mistake based upon my earlier understanding. Like they say, "The only stupid question is the one that is not asked.". So let me ask one more. Would a SLI configuration on a board that supports SLI give any advantage. I know they are physically bridged by a flat ribbon cable, but do not understand the impact of joining two GPUs in that fashion.
Edit: looking at the data for the 5 slot 3.0 X 16 Asus board you posted Mike, I have answered my question regarding SLI with respect to performance.
RE: It could have been a
)
I have made such a costly mistake, hence my prior research into the detail of the matter !! :-)
I'm not aware that SLI is relevant to E@H ...... anyone ???
Cheers, Mike.
( edit ) In addition to the lane count per link, there is also the speed of the lane ie. the clocking frequency of the LVDS ( Low Voltage Differential Signalling ) layer used. The problem with PCI, which is parallel hardware, was that the precise length of the signal lines comes into play at high clocking. One might send all signals ( of a parallel bus ) in clock sync from some source, but varying delays due to varying 'wire' lengths mean that some signal transitions arrive too late/early with respect to others, in order to be present as simultaneously valid at the destination. Some might 'miss the cut'. A pair of LVDS wires ( which constitute a receive or transmit portion of a full duplex serial connection ) carries no clocking signal per se. The PCIe standard mimics a parallel device by packetising data, in effect a form of multiplexing and demultiplexing. The assumption, and practice, is that the rather higher speed of the serial lanes outweighs the overhead of managing the packets.
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal
Count me in with three costly
)
Count me in with three costly mistakes working to run the fastest AMD host on the project ;)
AFAIK, Dual Display or SLI doesn't do anything good for BOINC, rather the opposite (at least in the old days this caused the then-current BOINC Versions to detect & use only one card).
Nowadays, it shouldn't make any difference - but the recommendation remained to keep Dual Display/SLI disabled in the Video Driver settings to avoid any issues.
I would also think linking them together would cause a tiny bit of overhead that can be avoided no matter how small it is.
Yeah, ya gotta beware the ad
)
Yeah, ya gotta beware the ad on the website or the sticker on the box. You might wind up buying a five-wheeled motorbike .... :-)
Cheers, Mike.
I have made this letter longer than usual because I lack the time to make it shorter ...
... and my other CPU is a Ryzen 5950X :-) Blaise Pascal